FPGA Implementation of JPEG2000 Arithmetic Encoder

JPEG2000 is the new emerging international standard for image compression that has been developed by JPEG (Joint Photographic Experts Group). It is far superior over many other compression standards like JPEG in terms of performance and feature set. The rich feature set makes it suitable in many multimedia applications but at the same time its high complexity makes it difficult to optimize the performances of some implementations. Hence this paper analyses the performance gain between the software and hardware implementation of JPEG2000 Arithmetic encoder which is the heart of image compression process. The main goal is to propose a new architecture for arithmetic encoder and to develop it in hardware description language along with synthesizing in Field Programmable Gate Array Xilinx. Index Terms – DWT,EBCOT,FPGA,MQ Encoder,multimedia.